1. Field of the Invention
This invention relates to circuits and methods for handling signals in a circuit such as a processor having two clock domains and to input and output cells for a processor.
2. Description of Related Art
Microprocessors commonly employ a system bus that operates at a fixed clock frequency according to an established bus protocol and a processing core that operates at a higher frequency selected according to circuit performance. For such microprocessors, bus signals for control, data, and address information are synchronized with a bus clock signal. Conventionally, input bus signals become valid somewhat before a triggering edge (conventionally a rising edge) of the bus clock signal and remain valid after the edge of the bus clock signal. The time between a bus signal being valid and a triggering edge of the bus clock signal is referred to as the set-up time of the bus signal. After the triggering edge, the bus signal remains valid for a period of time referred to as the hold time. The bus protocol defines required set-up and hold times for the variety of input bus signals.
In a processor, most bus signals must be resynchronized with a processor clock for the processing core. The processing core typically includes processing paths having several stages where each stage requires a processor clock cycle for processing. To resynchronize a signal and provide a full processor clock cycle for a stage, a memory element such as a flip-flop operated off the processor clock registers a signal from a circuit element operated off the bus clock and holds the signal for a full processor clock cycle. This is sometimes referred to as the signal crossing from the clock domain of the bus to the clock domain of the processing core. Similarly, memory elements clocked by the bus clock register signals from the processing core to resynchronize the core signals for output on the bus.
The processor clock is typically generated from the bus clock but has a different frequency from that of the bus clock signal. Depending on the relationship between the frequencies of the bus and processor clocks, some edges of the processor clock signal are approximately synchronized with edges of the bus clock signal. This approximate synchronization is subject to jitter and skew introduced by frequency multipliers, phase locked loops, and other circuits that generate or distribute the processor clock signal and the bus clock signal. Such jitter and skew creates a range of possible time separations between edges of the bus clock signal and edges of the processor clock signal. This can be a problem when a bus protocol requires short set-up and hold times for bus signals because the time during which a signal is valid may not sufficiently overlap the time required for registering the signal when the signal crosses between clock domains.
Input/output (I/O) cells for a processor commonly synchronize signals crossing between a clock domain operating at the bus clock frequency and the clock domain of the processing core. For resynchronization to be successful, the signal crossing between clock domains must have set-up and hold times that are sufficient to ensure that the signal has a valid value when registered into the new clock domain.
One class of bus signals, referred to herein as loop-back signals, includes input bus signals that immediately change a property of a processor. For example, a loop-back signal might control whether a specific pin or set of pins of a processor is for input or output during the bus clock cycle that begins at the edge of the bus clock signal to which the loop-back signal sets up. Thus, the effect of the loop-back signal starts at the edge at which the loop-back signal sets up (i.e., is valid). Known processors conventionally resynchronize a loop-back signal to inform the processing core of the state of a pin and pass the loop-back signal to the I/O cell for the pin. Resynchronizing the loop-back signal with the processor clock synchronizes the loop-back signal with any signals that I/O cell may require from the processing core. A result or combined effect of the loop-back signal and the required signals from the processing core must then be resynchronized with the bus clock in the I/O cell. The resynchronizations of such loop-back signals and jitter or skew between the processor clock and the bus clock constrain the required set-up and hold times for the loop-back signals. Processors that require short set-up and hold times for bus signals such as loop-back signals are sought.